Microarchitecture of HaL´s cache subsystem

HaL´s cache subsystem is designed to provide high memory bandwidth to the processor. The cache is non-blocking: the cache can service a new CPU request while four cache line refills are progressing in the background. The cache subsystem is also designed to handle speculative and out-of-order CPU requests. The cache-CPU interface protocol allows precise interrupts to be maintained under out-of-order completion. The cache design, as other parts in HaL´s PM1 module pays attention to reliability and availability (RAS). The design takes advantage of SPARC V9´s RED state feature, and allows the software to recover from certain hardware errors. In addition, the cache uses SECDED (Single Error Correction Double Error Detection) to protect its data store and parity to protect its tag store.