Analytic modeling of AC response to FET-level elements for CLY optimization

Minimizing circuit AC delay variations while maintaining power/performance is key for achieving high yielding products. The present work discusses an analytic model based approach for aligning the fundamental-FET electrical control and circuit-speed variability applied towards product screening. Such a model is proven to be effective in a manufacturing environment for predicting delay variation, and identifying the limiting process issues that drive our capability to achieve success in maximizing yield. The ability to understand circuit delay as it relates back to basic device measurements provides an ability to improve standard work in semiconductor manufacturing and realize continuous productivity enhancement.