Thermal FEA of inverter for optimization of active chip area

This paper presents a novel control method to improve the efficiency of three-phase inverters at partial load and a thermal FEA modelling approach to examine temperature distribution in a hardware prototype. The efficiency improvement is based on variation of the active chip area during inverter operation. Due to their geometric position on the heat sink cooling efficiency is not equal for all IGBTs. Using the thermal FEA model an algorithm for choosing the active chips is developed, taking into account the thermal cycling of the IGBTs and its effects on inverter life time. The test setup of a prototype designed to verify this approach is described as well.