Process and materials considerations for Pb-free flip chip packaging of 65nm Cu/low-k device

In this paper, we present the findings of a feasibility study to understand the impact of process and materials interaction in Pb-free flip chip package of 65nm Cu/low-k device. The concerns pertaining to Cu/low-k packaging were evaluated with successful demonstration of existing baseline assembly processes for low-k packaging. Several underfill materials were also evaluated in terms of processability and package reliability. The assembly and reliability results to date have been positive with no failures observed in the low-k dielectric layers. Reliability results suggest that with this test vehicle, the matching of underfill properties for low-k compatibility seemed to be less critical. The positive results are also indicative of the stability of the low-k layers structural design.