DocumentCode
2278568
Title
Design of a low power charge pump circuit for phase-locked loops
Author
Huili Xu ; Zhiqun Li
fYear
2012
fDate
10-11 May 2012
Firstpage
1
Lastpage
4
Abstract
In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18μm CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than ±0.005%. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V.
Keywords
CMOS integrated circuits; amplifiers; frequency synthesizers; phase locked loops; power consumption; CMOS process; current matching; low power charge pump circuit design; lower power PLL-based frequency synthesizer; phase-locked loops; power 0.56 mW; power consumption; voltage 0.3 V to 1.7 V; voltage 1.8 V; wide input ranged operational amplifier; CMOS integrated circuits; Charge pumps; Discharges (electric); MOS devices; Operational amplifiers; Phase frequency detector; Phase locked loops;
fLanguage
English
Publisher
ieee
Conference_Titel
High Speed Intelligent Communication Forum (HSIC), 2012 4th International
Conference_Location
Nanjing, Jiangsu
Print_ISBN
978-1-4673-0678-2
Electronic_ISBN
978-1-4673-0676-8
Type
conf
DOI
10.1109/HSIC.2012.6213018
Filename
6213018
Link To Document