Design of a low-voltage high-speed CMOS integer-M frequency divider in WSN applications

Author

Yu Lu ; Fan Xiangning

Author_Institution

Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China

fYear

2012

fDate

10-11 May 2012

Firstpage

1

Lastpage

4

Abstract

A 5GHz low-voltage CMOS integer-M frequency divider whose modulus can be varied from 2403 to 2480 for WSN applications is presented in this paper. The divider contains two blocks, a dual-modulus prescaler (DMP), which adopts the structure of the pseudo-differential static D-type flip-flop, and a pulse-swallow counter. The whole frequency divider is designed in 0.18μm CMOS process and the simulation results illustrate that the divider can operate normally over a wide range of 4-6 GHz which consumes 1.89mA at 1 V.

Keywords

CMOS integrated circuits; MMIC frequency convertors; flip-flops; frequency dividers; low-power electronics; wireless sensor networks; MMIC frequency convertors; current 1.89 mA; dual modulus prescaler; frequency 4 GHz to 6 GHz; low-voltage high-speed CMOS integer-M frequency divider; pseudo differential static D-type flip-flop; pulse swallow counter; size 0.18 mum; voltage 1 V; wireless sensor networks; CMOS integrated circuits; Computer architecture; Frequency conversion; Frequency synthesizers; Layout; Radiation detectors; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

High Speed Intelligent Communication Forum (HSIC), 2012 4th International

Conference_Location

Nanjing, Jiangsu

Print_ISBN

978-1-4673-0678-2

Electronic_ISBN

978-1-4673-0676-8

Type

conf

DOI

10.1109/HSIC.2012.6213023

Filename

6213023