• DocumentCode
    2279443
  • Title

    Multifault testability of delay-testable circuits

  • Author

    Ke, Wuudiann ; Menon, P.R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    400
  • Lastpage
    403
  • Abstract
    This paper investigates the relationship between path-delay-fault testability and multiple stuck-at-fault testability in multilevel combinational circuits. It is shown that a complete robust path-delay-fault test set may not detect all multiple stuck-at faults in multilevel circuits. We also show that path-delay-fault testability does not imply multiple stuck-at-fault testability in multilevel circuits, contradicting a recent paper. Certain path delay tests are also shown to be invalidated by the presence of untestable or untested multiple stuck-at faults
  • Keywords
    combinational circuits; delays; logic testing; multivalued logic circuits; delay-testable circuits; multifault testability; multilevel combinational circuits; multiple stuck-at-fault testability; path-delay-fault testability; robust path-delay-fault test set; Circuit faults; Circuit testing; Combinational circuits; Delay; Digital circuits; Electrical fault detection; Fault detection; Logic testing; Robustness; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1995. Proceedings., 13th IEEE
  • Conference_Location
    Princeton, NJ
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7000-2
  • Type

    conf

  • DOI
    10.1109/VTEST.1995.512667
  • Filename
    512667