3D Trigate 1T-DRAM Memory Cell for 2x nm Nodes

This paper presents a capacitor-less 1T DRAM cell based on a 3D Triple-gate multibody transistor with high scalability, low-power consumption, long retention time, non-destructive reading, and wide memory window. High performance is demonstrated on a 20nm channel length device, including ´1´ to ´0´ current ratio larger than 103 (with negligible ´0´ current level), very low voltage bias operation and retention time longer than 20ms at 85°C in worst cases. Compared to the previous equivalent 3D memory cells reported so far, the proposed cell shows longer retention time even though the gate length shrinks to the half of them. The voltages used to write and read the information is by far, much smaller than the previously reported ones in comparable structures. We have confirmed by TCAD simulation that the improvements are attributed to an innovative operation concept: a dedicated body partitioning.