DocumentCode
2282346
Title
Low- and ultra low-power arithmetic units: design and comparison
Author
Vratonjic, Milena ; Zeydel, Bart R. ; Oklobdzija, Vojin G.
Author_Institution
Adv. Comput. Syst. Eng. Lab. (ACSEL), California Univ., Davis, CA, USA
fYear
2005
fDate
2-5 Oct. 2005
Firstpage
249
Lastpage
252
Abstract
Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for these regions of operations. This paper demonstrates that the use of more complex high-performance structures combined with scaling of the supply-voltage outperforms traditional low-power oriented designs in the low- and ultra low-power domain.
Keywords
adders; digital arithmetic; integrated circuit design; logic design; low-power electronics; energy-delay space; supply voltage scaling; ultra low-power arithmetic units; Adders; Algorithm design and analysis; Arithmetic; Delay; Design engineering; Energy efficiency; Laboratories; Power engineering and energy; Systems engineering and theory; Wireless sensor networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.71
Filename
1524161
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