Exact lower bound for the number of switches in series to implement a combinational logic cell

This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that complementary series/parallel (CSP) and pass transistor logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that produces cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.