Performance of the ASP on the DARPA architecture benchmark

The associative string processor (ASP) is a homogeneous, reconfigurable, programmable massively parallel processor which offers step-function advantages in cost performance and application flexibility due to its unique architecture and its use of state-of-the-art microelectronics. The authors briefly describe the ASP architecture and its implementation and report the results of an evaluation of its applicability to image-processing tasks. In order to provide a realistic demonstration of the above-mentioned advantages, a set of independently defined tasks (viz. the Defense Advanced Research Projects Agency (DARPA) image-understanding benchmark) was chosen for the evaluation, and the results are used to compare the performance of the ASP architecture with the performances of other parallel computer architectures when applied to the same computer vision tasks