Control Gate Length, Spacing and Stacked Layer Number Design for 3D-Stackable NAND Flash Memory

Author

Yanagihara, Yuki ; Miyaji, Kousuke ; Takeuchi, Ken

Author_Institution

Dept. of Electr. Eng. & Inf. Syst., Univ. of Tokyo, Tokyo, Japan

fYear

2012

fDate

20-23 May 2012

Firstpage

1

Lastpage

4

Abstract

Scaling and device design for 3D-stackable NAND (3D NAND) flash memory are investigated. Control gate length (Lg) and spacing (Lspace) are paid attention since they can be separately varied in 3D NAND and significantly affect the cell area of the 3D NAND as well as the electrical characteristics. The requirements for the Lg and Lspace are derived from the 3D device simulation and the cell size to compete with the planar NAND. The simulations reveal that Lg=Lspace=20nm (40nm layer pitch) is achievable for BiCS type 3D NAND with the 90nm diameter hole. Programming voltage can be also reduced from 20V to 17V. Lg and Lspace should be the same to cope with the tradeoff between memory window and disturbance. If the number of stacked layers is 18 with the layer pitch of 40nm, the effective cell size of the 3D NAND corresponds to that of 15nm planar NAND technology.

Keywords

NAND circuits; circuit simulation; flash memories; integrated circuit design; low-power electronics; 3D device simulation; 3D-stackable NAND flash memory; bit-cost scalable; control gate length; device design; electrical characteristics; memory window; planar NAND technology; programming voltage; scaling; size 15 nm; size 20 nm; size 40 nm; size 90 nm; stacked layer number design; voltage 17 V; voltage 20 V; Electric fields; Flash memory; Logic gates; Programming; Solid modeling; Substrates; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2012 4th IEEE International

Conference_Location

Milan

Print_ISBN

978-1-4673-1079-6

Type

conf

DOI

10.1109/IMW.2012.6213656

Filename

6213656