DocumentCode
228299
Title
A 10-bit 25MSPS low power pipeline ADC for Mobile HDTV Receiver System
Author
Dongre, Krushna ; Akre, Pratik ; Kamdi, Rahul ; Sarangam, K.
Author_Institution
Dept. of Electron. & Tele-Commun. Eng., Yeshwantrao Chavan Coll. of Eng. Nagpur, Nagpur, India
fYear
2014
fDate
13-14 Feb. 2014
Firstpage
1
Lastpage
6
Abstract
This paper describes a 10-bit 25MSPS analog-to-digital converter (ADC) for Mobile HDTV Receiver System. The ADC is based on a 4-3-3 bits- per-stage pipeline architecture and The proposed pipelined ADC adopts a optimized stage resolution based on power consumption of sample and hold circuit and comparator. At the target sampling rate of 25MS/s, measured results show that the converter consumes 12.36mW from a 1.8V power supply and 56dB SNR and 60dB SFDR.
Keywords
analogue-digital conversion; comparators (circuits); high definition television; radio receivers; sample and hold circuits; analog-to-digital converter; comparator; low power pipeline ADC; mobile HDTV receiver system; optimized stage resolution; power 12.36 mW; power consumption; sample and hold circuit; voltage 1.8 V; Accuracy; Delays; Digital video broadcasting; HDTV; MOS devices; Receivers; Topology; ADC; HDTV Receiver; Low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics and Communication Systems (ICECS), 2014 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-2321-2
Type
conf
DOI
10.1109/ECS.2014.6892549
Filename
6892549
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