A novel differential 9t cell sram with reduced sub threshold leakage power

As the CMOS technology is being scaled down continuously, power dissipation is the major constraint for VLSI designers. In this paper we propose a differential 9T cell SRAM which employs differential read operation of cell as compared to conventional 8T cell SRAM without compromising with performance and stability. Moreover the proposed 9T SRAM uses a gated ground sleep transistor (nmos transistor inserted between ground line and SRAM cell) which reduces the sleep leakage power consumption 10 times as compared to the conventional 8T cell SRAM in the sleep mode. The differential operation of the proposed cell helps in keeping the other peripherals to be simple and consume low power. Results show read and write power of proposed cell is 33% and 35% reduced as compared to 8T cell SRAM. So along with the symmetrical design, differential read operation and gated ground, performance of the proposed design improves with reduced power and minimal area overhead.