Stochastic extraction for SoC and SiP interconnect with variability

In this paper we present two algorithms for capacitance and high-frequency impedance extraction for on-chip and on-package interconnect in the presence of random geometrical variations due to uncertainties in the manufacturing processes. The first algorithm, stochastic model reduction algorithm (SMOR), falls under the category of sampling based methods, also known as non-intrusive methods. The second algorithm, stochastic dominant singular vectors (SDSV), falls under the category of expansion based methods, also known as intrusive algorithms. Finally, we compare the presented algorithms to several state of the art solvers on several very large and complex examples.