PCB trace modeling and equalizer design method for 10 Gbps backplane

This paper discusses accurate PCB modeling methods for 10 Gbps differential signal traces. We added two approaches to the conventional modeling method: (1) We simulated the glass cloth and epoxy distribution in the PCB dielectric to simulate common/differential mode conversion noise (SCD21). (2) We applied a frequency-dependent dielectric constant to the electromagnetic analysis model based on a Djordjevic-Sarkar model to introduce a frequency-dependent group delay. Applying these two additional modeling elements, we obtained accurate SCD21 and jitter properties consistent with measurement results. We also demonstrated an equalizer design based on the improved PCB model. By flattening the frequency dependence of the group delay as well as trace losses for the transmission paths, including the equalizer, by adjusting the properties of the peaking amplifier for the equalizer circuit, we reduced jitter by up to 10 ps for 10 Gbps signalling.