A 32-bank 256 Mb DRAM with cache and TAG

Author

Tanoi, S. ; Tanaka, Y. ; Tanabe, T. ; Kita, A. ; Inada, T. ; Hamazaki, R. ; Ohtsuki, Y. ; Uesugi, M.

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

144

Lastpage

145

Abstract

Megabit DRAM design has recently focused both on high data transfer rates and battery operation. To meet the demand for high data-rate memory, this synchronously-operated 32-bank 256 Mb CMOS DRAM has sense amplifier (SA) cache strips and TAGs. The key techniques are: (1) high bit-rate cache operation achieved by 32 8 Mb memory banks supported by the bank-associated shared SA caches and TAG blocks embedded in row decoders, (2) a reduced RAS latency achieved during a bank hit cycle by a bank interleaving scheme, (3) high stability bank control by phase alignment of high-rate timing pulses, and (4) current sensing data-bus amplifier (CSA) scheme with a voltage-controlled negative conductance (VCNC) circuit.<>

Keywords

CMOS integrated circuits; DRAM chips; buffer storage; 256 Mbit; RAS latency; TAG blocks; bank interleaving scheme; current sensing data-bus amplifier; dynamic RAM; high stability bank control; high-rate timing pulses; megabit DRAM design; phase alignment; row decoders; sense amplifier cache strips; synchronously-operated 32-bank DRAM; voltage-controlled negative conductance circuit; Batteries; Circuit stability; Decoding; Delay; Interleaved codes; Pulse amplifiers; Random access memory; Strips; Technical Activities Guide -TAG; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344695

Filename

344695