Trading bandwidth for latency: managing continuations through a carpet bag cache

Processing-in-memory (PIM) circumvents the von Neumann bottleneck by combining logic and memory (typically DRAM) on a single die. This work examines the performance of a mobile thread execution model in which threads traverse the system\´s address space in search of their required data over a massively parallel PIM array targeted at petaFLOP performance. This model is enabled through the use of a carpetbag cache which travels with the thread and provides data from the node previously visited. In this way, the latency of traveling to a node already visited is avoided by paying the additional bandwidth and packaging costs associated with moving the cache. Furthermore, it is shown that thrashing between two nodes will generally occur without the use of the cache. Each of the simulations conducted in this work was conducted under stress. By using the Data Intensive Systems (DIS) benchmark suite, the model was subjected to "worst case" memory access patterns, and ultimately still proved highly successful. Additionally, it is shown that this model caters to the positive aspects of a PIM - specifically, the very fast local memory access available.