A 100 MHz, 5MBaud QAM decision-feedback equalizer for digital television applications

Author

Joshi, R.B. ; Samueli, H.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

68

Lastpage

69

Abstract

The single-chip 5Mbaud DFE-based adaptive equalizer for QAM receivers presented in this paper may be used with an A/D converter, demodulator and carrier and timing recovery loop to construct an all-digital general-purpose QAM receiver. The QAM adaptive equalizer chip accommodates 4-, 16-, 64-, and 256-QAM formats, and incorporates a 20-tap feed-forward equalizer (FFE) and a a 2O-tap decision-feedback equalizer (DFE). The FFE can perform either T-spaced or T/2-spaced equalization. The maximum clock rate of the chip is over 100MHz, where the equalizer operates at maximum symbol rate of 5Mbaud, corresponding to throughputs of 10, 20, 30, and 40Mb/s for 4-, 16-, 64-, and 256-QAM, respectively. The chip occupies 9.8x6.7mm/sup 2/ die area in a 1.O /spl mu/m CMOS process.<>

Keywords

CMOS integrated circuits; amplitude modulation; digital communication systems; equalisers; television receivers; 1.0 micron; 100 MHz; A/D converter; CMOS process; all-digital QAM receiver; carrier recovery loop; clock rate; decision-feedback equalizer; demodulator; digital television; feed-forward equalizer; single-chip 5Mbaud adaptive equalizer; symbol rate; timing recovery loop; Adaptive equalizers; Clocks; Decision feedback equalizers; Digital TV; Feedforward systems; Finite impulse response filter; HDTV; Hardware; Quadrature amplitude modulation; Reflection;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344723

Filename

344723