• DocumentCode
    2286933
  • Title

    SiO2/Si3N4 bilayer sloped etching for 20nm InAlAs/InGaAs metamorphic HEMTs

  • Author

    Kim, Jongwook ; Lee, Minseong ; Seo, Kwangseok

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Universify, Seoul, South Korea
  • fYear
    2010
  • fDate
    17-20 Aug. 2010
  • Firstpage
    246
  • Lastpage
    249
  • Abstract
    We developed a 20 nm gate process using SiO2/Si3N4 bilayer sloped etching. Selective and sloped etching of bilayer makes this technology realizable. A HEMT with this technology has merits of fine length definition beyond the limit of electron beam (E-beam) lithography system. Using this technology, we experimentally demonstrated that a 20 nm gate length from initial 50 nm line pattern. The fabricated InAlAs/InGaAs metamorphic HEMTs (MHEMTs) with 20 nm T-gate pattern have high DC and RF performance characteristics, a transconductance of 1.67 S/mm, a cutoff frequency ft of 460 GHz.
  • Keywords
    III-V semiconductors; aluminium compounds; etching; gallium arsenide; high electron mobility transistors; indium compounds; DC characteristics; In0.75AlAs-In0.52GaAs; RF performance characteristics; SiO2-Si3N4; T-gate pattern; bilayer sloped etching; gate length; gate process; metamorphic HEMT; size 20 nm; transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology (IEEE-NANO), 2010 10th IEEE Conference on
  • Conference_Location
    Seoul
  • ISSN
    1944-9399
  • Print_ISBN
    978-1-4244-7033-4
  • Electronic_ISBN
    1944-9399
  • Type

    conf

  • DOI
    10.1109/NANO.2010.5697890
  • Filename
    5697890