• DocumentCode
    228753
  • Title

    Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications

  • Author

    Ashari, Arash ; Sedaghati, Naser ; Eisenlohr, John ; Parthasarath, Srinivasan ; Sadayappan, P.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Ohio State Univ., Columbus, OH, USA
  • fYear
    2014
  • fDate
    16-21 Nov. 2014
  • Firstpage
    781
  • Lastpage
    792
  • Abstract
    Sparse matrix-vector multiplication (SpMV) is a widely used computational kernel. The most commonly used format for a sparse matrix is CSR (Compressed Sparse Row), but a number of other representations have recently been developed that achieve higher SpMV performance. However, the alternative representations typically impose a significant preprocessing overhead. While a high preprocessing overhead can be amortized for applications requiring many iterative invocations of SpMV that use the same matrix, it is not always feasible -- for instance when analyzing large dynamically evolving graphs. This paper presents ACSR, an adaptive SpMV algorithm that uses the standard CSR format but reduces thread divergence by combining rows into groups (bins) which have a similar number of non-zero elements. Further, for rows in bins that span a wide range of non zero counts, dynamic parallelism is leveraged. A significant benefit of ACSR over other proposed SpMV approaches is that it works directly with the standard CSR format, and thus avoids significant preprocessing overheads. A CUDA implementation of ACSR is shown to outperform SpMV implementations in the NVIDIA CUSP and cuSPARSE libraries on a set of sparse matrices representing power-law graphs. We also demonstrate the use of ACSR for the analysis of dynamic graphs, where the improvement over extant approaches is even higher.
  • Keywords
    graph theory; graphics processing units; mathematics computing; matrix multiplication; parallel architectures; ACSR; CSR format; CUDA implementation; GPUs; NVIDIA CUSP libraries; SpMV approach; adaptive SpMV algorithm; compressed sparse row; computational kernel; cuSPARSE libraries; dynamic graphs; dynamic parallelism; fast sparse matrix-vector multiplication; graph applications; iterative invocations; power-law graphs; thread divergence; Heuristic algorithms; Instruction sets; Kernel; Parallel processing; Sparse matrices; Standards; Vectors; ACSR; CSR; GPU; HYB; SpMV;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing, Networking, Storage and Analysis, SC14: International Conference for
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    978-1-4799-5499-5
  • Type

    conf

  • DOI
    10.1109/SC.2014.69
  • Filename
    7013051