An algorithm for the design of low power linear phase FIR filters

In this work, a novel algorithm is proposed for the design of low power linear phase finite impulse response (FIR) filters with discrete coefficients. The proposed algorithm finds an adder and shift network using a small logic depth to realize the coefficient multipliers. This is achieved by constraining the synthesis of each coefficient on its minimum adder depth. The new synthesis mechanism tends to use a few more adders to successfully realize the discrete filter coefficients than the current best algorithms, but with lower average logic depth, resulting in a low power implementation. Designs of benchmark filters and simulation results verified the above claims.