A robust design for ultra low power operation using dynamic threshold SCL logic

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed a dynamic threshold source coupled logic and analyses the performance of dynamic threshold source coupled logic with previous source coupled logic for ultra low power operation. Dynamic threshold source coupled logic circuits exhibit a better power-delay Performance compared with the Sub-threshold Source Coupled Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control on power dissipation [1]. Measurements of test structures are simulated in 0.18 μm CMOS technology show that the proposed dynamic threshold source coupled l logic concept can be utilized successfully for bias currents as low as 1 pA[2]. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits.