SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

Author

Delprat, Daniel ; Boedt, François ; David, Carole ; Reynaud, Patrick ; Alami-Idrissi, Aziz ; Landru, Didier ; Girard, Christophe ; Maleville, Christophe

Author_Institution

SOITEC SA, Crolles, France

fYear

2009

fDate

5-8 Oct. 2009

Firstpage

1

Lastpage

4

Abstract

Fully depleted (FD) MOSFET architecture for sub-32 nm technology node requires a new SOI substrate fabrication to meet all the stringent specifications imposed by a FD device. Ultra thin SOI (UTSOI) targets planar device architectures, stressing specifications for thickness uniformity. Also ultra thin burried oxyde (UTBOx) offers additional benefits such as the application of back bias, for example enhancing device stability or threshold voltage tuning. In this paper, we discuss the Smart Cuttrade technology capability for both UTSOI and UTBOx substrate design with the quality and specifications that meet the future FD technology requirements.

Keywords

MOSFET; silicon-on-insulator; MOSFET architecture; SOI substrate readiness; Smart Cut technology capability; fully depleted planar device architectures; size 32 nm; ultra thin SOI; ultra thin burried oxyde; Fabrication; MOSFET circuits; Manufacturing; Microprocessors; Production; Silicon; Stability; Substrates; Thickness control; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2009 IEEE International

Conference_Location

Foster City, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-4256-0

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2009.5318744

Filename

5318744