Design of multilevel mixed-mode simulator for LSI/VLSI circuits

Author

Dabrowski, Jerzy

Author_Institution

Inst. of Electron., Silesian Tech. Univ., Gliwice, Poland

fYear

1988

fDate

7-9 Jun 1988

Firstpage

1635

Abstract

A prototype mixed-mode simulator (HYBRID) combines the speed of the conventional logic simulation with the accuracy of the block waveform relaxation method. A unified simulation time is introduced so that two subsimulators can work within one selective trace and next-event relaxation process. The simulator makes use of a multilevel macromodeling technique particularly well-suited to the block waveform relaxation. Logic and circuit types of macromodels are used. For typical logic MOS structures, a type specification algorithm based on the electrical loading effect (coupling of nodes) is proposed

Keywords

MOS integrated circuits; VLSI; hybrid simulation; integrated logic circuits; logic CAD; LSI/VLSI circuits; accuracy; block waveform relaxation; electrical loading effect; logic MOS structures; logic simulation; macromodels; multilevel mixed-mode simulator; speed; subsimulators; type specification algorithm; Circuit analysis computing; Circuit simulation; Computational modeling; Coupling circuits; Discrete event simulation; Electronic circuits; Large scale integration; Logic circuits; Very large scale integration; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.15247

Filename

15247