DocumentCode
2291648
Title
LDD depletion effects in thin-BOX FDSOI devices with a ground plane
Author
Yan, R. ; Duane, R. ; Razavi, P. ; Afzalian, A. ; Ferain, I. ; Lee, C.-W. ; Dehdashti-Akhavan, N. ; Bourdelle, K. ; Nguyen, B.Y. ; Colinge, J.P.
Author_Institution
Tyndall Nat. Inst., Cork, Ireland
fYear
2009
fDate
5-8 Oct. 2009
Firstpage
1
Lastpage
2
Abstract
In this paper, we analyze LDD depletion effects in fully-depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15 nm.
Keywords
silicon-on-insulator; thin film devices; LDD depletion effects; drain resistance; ground plane; short-channel effects; silicon-on-insulator; source resistance; thin-BOX FDSOI devices; threshold voltage shifts; CMOS technology; Electrostatics; Fluctuations; Hafnium oxide; MOSFETs; Semiconductor device modeling; Thickness control; Thin film devices; Threshold voltage; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2009 IEEE International
Conference_Location
Foster City, CA
ISSN
1078-621X
Print_ISBN
978-1-4244-4256-0
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2009.5318771
Filename
5318771
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