• DocumentCode
    2291725
  • Title

    Effect of source/drain asymmetry on the performance of Z-RAM® devices

  • Author

    Mohapatra, N.R. ; vanBentum, R. ; Pruefer, E. ; Maszara, W.P. ; Caillat, C. ; Chalupa, Z. ; Johnson, Z. ; Fisch, D.

  • Author_Institution
    AMD Fab36 LLC & Co. KG, Dresden, Germany
  • fYear
    2009
  • fDate
    5-8 Oct. 2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper, the performance of Zero capacitor RAM (Z-RAMreg) devices, developed in a 45 nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much better memory performance compared to the symmetrically doped Z-RAM (SD) devices.
  • Keywords
    CMOS memory circuits; random-access storage; silicon-on-insulator; SOI CMOS technology; asymmetric doping; size 45 nm; source-drain assymetry; symmetric doping; zero capacitor RAM; CMOS technology; Cache memory; Circuits; Feedback loop; Impact ionization; Implants; Read-write memory; Silicon; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2009 IEEE International
  • Conference_Location
    Foster City, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-4256-0
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2009.5318778
  • Filename
    5318778
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2291725