Memory circuits for multiple valued logic voltage signals

Voltage-mode CMOS multiple valued logic memory circuits have been realized in a standard 2-micron p-well polysilicon-gate CMOS technology. These circuits requantize multiple-valued logical voltages during a SETUP clock mode and latch the input value during the HOLD clock mode. Using a 5 volt supply and logical voltage increments of 1.67 volts, two similar quaternary memory circuits have worst-case total SETUP and HOLD times of about 5.7 ns and 7 ns; and best single-level transition total SETUP and HOLD times of about 0.9 ns and 1 ns