Peak current estimation for digital filters

Estimates of the peak power dissipation and the peak current are required in the design of reliable VLSI circuits. The peak current current drawn by a digital filter is dependent on the filter coefficients and the inputs to the multipliers in the filter. This input dependence makes the estimation of peak current for a digital filter a hard problem. We present a technique to estimate the maximum current drawn by a digital filter. The approach consists of: (1) building peak current macro-models for multipliers in terms of the input data transitions and the coefficient, and (2) using these models in a graph based formulation for finding the peak current of the digital filter. The peak current macro-models for multipliers are validated by comparisons with SPICE simulations. We also present the application of the technique for estimating the peak current of digital filters in a 51.84 Mb/s 16-CAP receiver