Improved built-in test pattern generators based on comparison units for synchronous sequential circuits

We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determination of the test sequence applied to the circuit-under-test, using fewer logic gates than the original scheme. In addition, a procedure to match the parameters of the test pattern generator to the circuit-under-test is proposed to replace the random selection used in the basic scheme. The effectiveness of these improvements is demonstrated through experimental results