FPGA based pipelined architecture for RC5 encryption

The reconfigurable processors like FPGA are extensively used for cryptographic applications which have reduced the time to market of the hardware logic. This paper describes the high performance pipelined hardware implementation of RC5 algorithm in Xilinx Vertex II Pro FPGA with a 12-stage pipeline scheme that has achieved an encryption rate of 6.9 Gbps. The proposed design operates on 12 input data and a common key where each clock signal produces a partial single round encryption output. After 12 clocks cycles, the cipher text of the corresponding input data is derived at the output sequentially for every clock transition. The pipelined hardware was implemented and the efficiency was compared with the other versions of RC5.