A zone based self repairing SRAM architecture using adaptive body biasing schemes

In nano scale devices, the major barrier that the CMOS devices face is increasing process parameter variations. The inter-die and intra-die variations in process parameters results in large number of failures in area constrained circuits such as SRAM cell, thus degrading the design yield. Adaptive repairing techniques such as adaptive body bias reduce the failure probabilities thus increasing the design yield. To apply this technique we have to distinguish between the dies from low-Vt process corners and those from high-Vt process corners. In this paper, we propose a new zone based repairing scheme for the dies, which fall in high-Vt corner by which the efficiency of the adaptive repairing technique can be improved.