DocumentCode
2304876
Title
CMOS-photonic “macrochip” packaging
Author
Thacker, Hiren D. ; Shubin, Ivan ; Zheng, Xuezhe ; Costa, Joannes ; Luo, Ying ; Li, Guoliang ; Yao, Jin ; Shi, Jing ; Lexau, Jon ; Ho, Ron ; Raj, Kannan ; Mitchell, James G. ; Cunningham, John E. ; Krishnamoorthy, Ashok V.
Author_Institution
Sun Labs., Oracle, San Diego, CA, USA
fYear
2010
fDate
7-11 Nov. 2010
Firstpage
485
Lastpage
486
Abstract
Two novel packaging technologies have been developed to serve as essential building blocks for construction of a photonically interconnected large-chip array. Ultralow parasitic microsolder interconnections (on the order of 100 mOhm/bump and 25 fF/bump) allow combination of best-in-class chips, which may be built on different technology platforms, and CMOS compatible ball-in-etch-pit structures provide a non-permanent passive selfaligning mechanism for highly accurate componentto-component placement.
Keywords
integrated optics; integrated optoelectronics; packaging; macrochip; packaging; parasitic microsolder interconnections; photonically interconnected largechip array;
fLanguage
English
Publisher
ieee
Conference_Titel
IEEE Photonics Society, 2010 23rd Annual Meeting of the
Conference_Location
Denver, CO
ISSN
-
Print_ISBN
978-1-4244-5368-9
Electronic_ISBN
-
Type
conf
DOI
10.1109/PHOTONICS.2010.5698972
Filename
5698972
Link To Document