Low-cost patterned metallization technique for high density multilayer interconnect applications

Fabrication of high density multilayer hybrids such as multichip modules (MCMs) incorporates thin film metallization techniques to produce conductor layers. Highly uniform, fine line metallization patterns must be produced to achieve high speed, low-loss performance requirements. The widely used metallization processes contribute substantially to both fabrication costs and to initial capital equipment expenditures and operating expenses. Careful consideration, therefore, must be made in the selection of a metallization process with the capability to meet product requirements and the flexibility to address market changes. This paper presents preliminary work on the use of a vacuum deposition process known as enhanced ion-plating (EIP) for conductor metallization of high density multilayer substrates