Package related reliability investigation with a multi-sensor chip

Author

Van Gestel, Rehard ; Van Gemert, Leo ; Bagerman, Eef

Author_Institution

Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1993

fDate

1-4 Jun 1993

Firstpage

391

Lastpage

395

Abstract

To perform IC package related reliability research a test chip has been developed containing a large number of test structures. The structures are connected to multiplexing logic for performing electrical measurements. The chips have been used in a case study where PLCC 68 devices were stressed with a 500 Temperature Cycle Test and a 300 hours Highly Accelerated Stress Test. All the test structures are sensitive for open/short failures and were measured to monitor their behaviour. Acoustical scanning of the packages was used to measure die-surface delamination. The measurement of chip-package reliability is discussed in relation to the variance of the measurement results over the used chips in these reliability tests

Keywords

acoustic imaging; circuit reliability; failure analysis; integrated circuit testing; life testing; packaging; 300 h; IC package; PLCC 68 devices; acoustical scanning; die-surface delamination; electrical measurements; highly accelerated stress test; multi-sensor chip; open failures; reliability; short failures; temperature cycle test; test chip; test structures; Acoustic measurements; Acoustic testing; Electric variables measurement; Integrated circuit packaging; Integrated circuit testing; Life estimation; Logic devices; Performance evaluation; Semiconductor device measurement; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1993. Proceedings., 43rd

Conference_Location

Orlando, FL

Print_ISBN

0-7803-0794-1

Type

conf

DOI

10.1109/ECTC.1993.346817

Filename

346817