Comprehensive analysis of delay in UDSM CMOS circuits

Author

Samanta, Jagannath ; De, Bishnu Prasad

Author_Institution

Dept. of ECE, Haldia Inst. of Technol., Haldia, India

fYear

2011

fDate

12-13 Sept. 2011

Firstpage

29

Lastpage

32

Abstract

In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on n^th power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), etc which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 input CMOS NAND and NOR gate. Our result is better than nth power law and Cadence (UMC90nm) simulation result with respect to both quality and estimation time. Our proposed model gives an average error of only 3.63% with compare to Cadence Simulation result.

Keywords

CMOS integrated circuits; CMOS logic circuits; invertors; logic gates; CMOS NAND gate; CMOS NOR gate; MOSFET model; UDSM CMOS circuit; body bias effect; cadence simulation; channel length modulation effect; delay model; drain induced barrier lowering; ultra deep submicron CMOS inverter; ultra deep submicron MOS device; velocity saturation effect; CMOS integrated circuits; Delay; Integrated circuit modeling; Inverters; Logic gates; MOSFET circuits; Semiconductor device modeling; BSIM; CMOS inverter; Sakuari Delay Model; UDSM; Vel ocity Sat ur ation effect;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communication and Computing Technologies (ICECCT), 2011 International Conference on

Conference_Location

Pauls Nagar

Print_ISBN

978-1-4577-1895-3

Type

conf

DOI

10.1109/ICECCT.2011.6077064

Filename

6077064