DocumentCode
2307627
Title
VLSI implementation of sorting network for ACSFD in WSN
Author
Baskaran, K. ; Raghu, M. ; Kumar, R. Rajendra
Author_Institution
Dr. Pauls Eng. Coll., Villupuram, India
fYear
2011
fDate
12-13 Sept. 2011
Firstpage
116
Lastpage
119
Abstract
A fault-tolerant distributed decision fusion in the presence of sensor faults via Collaborative Sensor Fault Detection (CSFD) was used traditionally. CSFD scheme is proposed in which the results of a homogeneity test are used to identify the faulty nodes within the network such that their quantized messages can be filtered out when estimating the parameter of interest. The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a stand-alone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the Approximated Collaborative Sensor Fault Detection (ACSFD) scheme and its VLSI architecture. Sorting operation are required in ACSFD to find out four biggest faulty node indexes for subsequent usage for this purpose. we have implemented different sorting algorithm to evaluate the efficiency of the sorting network.
Keywords
VLSI; fault diagnosis; fault tolerance; parameter estimation; power consumption; sensor fusion; sorting; wireless sensor networks; ACSFD scheme; ASIC; VLSI architecture; VLSI implementation; approximated collaborative sensor fault detection scheme; decision fusion scheme; fault-tolerant distributed decision fusion; faulty node indexes; faulty nodes; fusion center; hardware cost; homogeneity test; parameter estimation; power consumption; quantized messages; real-time WSN applications; sensor faults; sorting algorithm; sorting network; sorting operation; stand-alone device; Algorithm design and analysis; Circuit faults; Computer architecture; Educational institutions; Sorting; Very large scale integration; Wireless sensor networks; Decision Fusion; Sensor Fault Detection; Sensor Networks; VLSI Architecture; Wireless Networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communication and Computing Technologies (ICECCT), 2011 International Conference on
Conference_Location
Pauls Nagar
Print_ISBN
978-1-4577-1895-3
Type
conf
DOI
10.1109/ICECCT.2011.6077081
Filename
6077081
Link To Document