Path coverage based functional test generation for processor marginality validation

Functional test content to screen for electrical marginalities during silicon validation are not generated with the goal of identifying speed-limiting paths, adversely affecting the quality and efficiency of validation. We propose a methodology to generate functional tests to excite pre-silicon timing-critical paths along with environmental effects such as voltage droop. These tests are to replace random/function-targeted content as the source for identifying speed failures during silicon validation. The effectiveness of this methodology is demonstrated through silicon experiments on a recent processor.