Delay insensitive NCL reconfigurable logic

In an effort to design a delay insensitive reconfigurable logic device, Theseus Logic has developed a field programmable gate array based on the Atmel AT40K family of programmable logic devices. The asynchronous design techniques surrounding the use of convention logic remove and/or restrict the need for a global clock network. The gates associated with the logic functions switch only when processing data, effectively reducing the system power, bus noise and electromagnetic interference. Since the FPGA is delay insensitive and power efficient, the number of devices used can be scaled according to implementation demands without impacting system integration. In addition, circuits of one design can be easily ported to others or the entire design can be converted to an application specific integrated circuit design flow without concern for timing closure problems. Using Theseus Logic´s patented convention logic as a means of expressing the logic functions within the FPGA´s macrocells, a reconfigurable, delay insensitive, asynchronous digital implementation was achieved.