Design of a low power high speed auto-zeroed column-level ADC for data readout of CMOS APS based vertex detector

CMOS active pixel sensors have been proved to be promising technique for next generation vertex detector. As a good spatial resolution is required by the vertex detector, a column-based fully offset compensated 5-bit Analog-to-Digital Converter has been designed. The ADC is based on successive approximation architecture. In order to avoid use a large binary capacitor array, multiple references are used. Charge redistribution is achieved by applying different reference voltages. All the three dynamic reference voltages are independent and adjustable externally, which gives access to compensate the undesirable errors bit by bit. An external adjustable threshold value is used for triggering the conversion. An auto-zeroed sample and hold block has been designed to work in parallel with the ADC so that pipeline delay is avoided. The size of the whole system is 25 mum times 1 mm. Simulation results show that the sampling rate reaches 4 MSa/s and the power dissipation of analog components is less than 300 muW while working.