Finite wordlength design for VLSI FFT processors

Resource efficient FFT processors have become a common requirement for high-speed xDSL and OFDM transceivers. Hardwired VLSI implementations often result in smaller area and lower power consumption than general-purpose DSP processors. For hardwired designs, intelligent wordlength selection can be employed to further reduce hardware resource requirements. This paper describes a technique for quick and accurate estimation of FFT noise performance by modeling the FFT as a series of amplifier stages. The technique is employed to specify wordlengths that provide good tradeoffs between noise performance and hardware requirements. The technique is also used to show that the decimation-in-time radix-2 FFT algorithm has better finite wordlength properties than the decimation-in-frequency radix-2 FFT algorithm.