Symmetric CMOS in fully-depleted silicon-on-insulator using P/sup +/-polycrystalline SiGe gate electrodes

Author

Kistler, N. ; Woo, J.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

727

Lastpage

730

Abstract

In this work, polycrystalline SiGe gate electrodes have been implemented on fully-depleted silicon-on-insulator with light channel doping. Symmetric NMOS and PMOS operation is achieved, with threshold voltages in the range of 0.4-0.6 V. The devices exhibit good short-channel behavior and near-ideal subthreshold slope. CMOS ring oscillators with enhancement-mode NMOS and PMOS have been fabricated, exhibiting propagation delays comparable to previously reported values for fully-depleted SOI.<>

Keywords

CMOS integrated circuits; Ge-Si alloys; VLSI; insulated gate field effect transistors; integrated circuit technology; semiconductor doping; semiconductor materials; semiconductor-insulator boundaries; silicon; 0.4 to 0.6 V; P/sup +/-polycrystalline SiGe gate electrode; SiGe; VLSI; enhancement-mode NMOS; enhancement-mode PMOS; fully-depleted silicon-on-insulator; light channel doping; near-ideal subthreshold slope; propagation delays; ring oscillators; short-channel behavior; symmetric CMOS; threshold voltages; Doping; Electrodes; Germanium silicon alloys; MOS devices; Propagation delay; Silicon devices; Silicon germanium; Silicon on insulator technology; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347210

Filename

347210