• DocumentCode
    2312500
  • Title

    Single event gate rupture of power DMOS transistors

  • Author

    Darwish, M.N. ; Shibib, M.A. ; Pinto, M.R. ; Titus, J.L.

  • Author_Institution
    AT&T Bell Labs., Allentown, PA, USA
  • fYear
    1993
  • fDate
    5-8 Dec. 1993
  • Firstpage
    671
  • Lastpage
    674
  • Abstract
    Single Event Gate Rupture (SEGR) failure mechanism in power DMOS transistors is investigated experimentally and via numerical simulations. An increase in surface field at the surface is shown to be capable of causing SEGR. Modified DMOS transistors with thick gate oxide are shown to have consistent higher SEGR V/sub DS/ threshold.<>
  • Keywords
    failure analysis; insulated gate field effect transistors; power transistors; reliability; simulation; failure mechanism; numerical simulations; power DMOS transistors; single event gate rupture; surface field; thick gate oxide; Acceleration; Circuit testing; Current measurement; Energy exchange; Failure analysis; Leakage current; MOSFETs; Scanning electron microscopy; Threshold voltage; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
  • Conference_Location
    Washington, DC, USA
  • ISSN
    0163-1918
  • Print_ISBN
    0-7803-1450-6
  • Type

    conf

  • DOI
    10.1109/IEDM.1993.347223
  • Filename
    347223
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2312500