DocumentCode
2313186
Title
A 25 MHz Viterbi FEC codec
Author
Kerr, Richard ; Dehesh, Houtan ; Bar-David, Ayal ; Werner, David
Author_Institution
Qualcomm Inc., San Diego, CA, USA
fYear
1990
fDate
13-16 May 1990
Abstract
An implementation of a single-chip Viterbi codec which incorporates many features into a single device is described. The device also implements a unified trellis decoder using the industry standard convolutional codes to achieve good coding gain using phase-shift keying (PSK) trellis encoding. The level of integration and the device speeds present a new upper bound on system performance based on convolutional coding systems. The device was produced by silicon-compiler-based tools in 15 months
Keywords
CMOS integrated circuits; VLSI; application specific integrated circuits; codecs; 25 MHz; PSK; Viterbi FEC codec; convolutional coding systems; features; forward error correction; implementation; industry standard convolutional codes; level of integration; phase-shift keying; silicon-compiler-based tools; single-chip Viterbi codec; trellis encoding; unified trellis decoder; Bit error rate; Circuits; Codecs; Convolution; Convolutional codes; Decoding; Finite impulse response filter; Forward error correction; Signal to noise ratio; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124729
Filename
124729
Link To Document