New Design Technique of Dual-Output Second Generation Current Conveyor

Author

Motlak, Hassan Jassim ; Ahmad, S.N.

Author_Institution

Dept. of Electron. & Commun., F/O Eng. & Technol., New Delhi

fYear

2008

fDate

16-18 July 2008

Firstpage

424

Lastpage

429

Abstract

In this paper, a new dual-output second generation current conveyor (DO-CCII) circuit based-on resistive compensation technique is proposed. The resistive compensation technique is very simple and powerful technique used to improve bandwidth of CMOS DO-CCII without extra power consumption. PSpice simulations for MIETEC 0.5 mum CMOS technology show that the current mode and voltage mode bandwidths are respectively 2.3 GHz and 3.3 GHz, with power consumption of 2 mW. The simulation results have been included which confirm the desired results.

Keywords

CMOS integrated circuits; SPICE; compensation; current-mode circuits; integrated circuit design; power consumption; CMOS DO-CCII; PSPICE simulation; dual-output second generation current conveyor circuit; frequency 2.3 GHz; frequency 3.3 GHz; power 2 mW; power consumption; resistive compensation; size 0.05 mum; Bandwidth; CMOS technology; Circuit simulation; Current mode circuits; Energy consumption; Frequency; Mirrors; Operational amplifiers; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Trends in Engineering and Technology, 2008. ICETET '08. First International Conference on

Conference_Location

Nagpur, Maharashtra

Print_ISBN

978-0-7695-3267-7

Electronic_ISBN

978-0-7695-3267-7

Type

conf

DOI

10.1109/ICETET.2008.125

Filename

4579937