Heterostructure FETs for high speed applications

Author

Pei, S.S.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1988

fDate

7-9 June 1988

Abstract

Summary form only given. The optimization of heterostructure FET (HFET) structures for digital applications is described. By trading some of the 2-D electron-gas density for better pinch-off characteristics, HFETs with high current driving capability and low subthreshold voltage leakage current can be achieved with an optimized single-quantum-well channel structure. In addition, an HFET structure and a self-aligned ion implantation process designed for fabricating both E-FETs and D-FETs at the same time are proposed. Excellent threshold voltage uniformity on a wafer and good reproducibility from wafer to wafer, which meet the requirements of LSI circuits, are expected.<>

Keywords

digital integrated circuits; field effect integrated circuits; field effect transistors; ion implantation; large scale integration; 2D electron gas density; HFET; LSI circuits; digital IC; digital applications; heterostructure FET; high current driving capability; high speed applications; low subthreshold voltage leakage current; pinch-off characteristics; self-aligned ion implantation; single-quantum-well channel structure; FETs; HEMTs; Ion implantation; Large scale integration; Leakage current; Low voltage; MODFETs; Process design; Reproducibility of results; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15265

Filename

15265