Design of Multi-channel Dual-frequency Digital Receiver based on FPGA

FPGAs provide lots of the flexibility of programmable DSP processors but with higher real-time performance. An FPGA based on Multi-channel Dual-frequency Digital Receiver has been developed for Soft Radar. In this paper, we review digital down-conversion (DDC) technique, and a parallel processing architecture based on FPGA is introduced. The FPGA adopt block-based design, which consists of the ADC-Interface Module, the DDC Module, and the DSP-Interface Module. The overall multi-channel DDC processing is implemented in Xilinx Virtex-6 FPGA and has been applied to a radar system. The experimental result also indicates that the digital receiver has achieved a feasible performance.