Cell technology directions for advanced MPUs and other memory-embedded logic devices

Author

Kinugawa, M. ; Kakumu, M.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

37

Lastpage

40

Abstract

In this paper, a guideline for optimum embedded memory structures for advanced MPUs and other memory-embedded logic devices is proposed. It is concluded that introduction of full CMOS cells is inevitable for future SRAMs operated under reduced power supply voltage conditions. Therefore, MPUs will continue to use full CMOS cells maintaining excellent process and transistor design compatibility with SRAMs. On the other hand, some advanced logic devices will use DRAM cells, since they require higher density rather than higher performance or better process compatibility.<>

Keywords

CMOS integrated circuits; DRAM chips; SRAM chips; logic circuits; logic devices; microprocessor chips; CMOS cells; DRAM cells; SRAMs; advanced MPUs; advanced logic devices; cell technology; full CMOS cells; higher density; higher performance; memory-embedded logic devices; multiprocessor units; optimum embedded memory structures; process compatibility; reduced power supply voltage conditions; transistor design compatibility; Driver circuits; Guidelines; Logic devices; Power supplies; Process design; Random access memory; Semiconductor devices; Thin film transistors; Threshold voltage; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347404

Filename

347404