Performance of the 3-D sidewall flash EPROM cell

Author

Pein, H.B. ; Plummer, J.D.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

11

Lastpage

14

Abstract

We report on the performance of a promising new 3-D sidewall flash EPROM cell that has been implemented in a novel memory array. The 3-D flash EPROM is a vertical stacked gate cell with both floating and control gates surrounding a silicon pillar. The cell size is within 10% of the square of the minimum pitch and can be scaled without encountering punchthrough or isolation constraints. The cell has fast write and erase speeds and is suitable for 5V only operation. Read current is 3/spl times/ that of an equivalent generation conventional NOR-type cell.<>

Keywords

EPROM; VLSI; integrated memory circuits; silicon; 3D sidewall flash EPROM cell; 5V only operation; cell size; control gates; fast erase speeds; fast write speeds; floating gates; isolation constraints; memory array; minimum pitch; punchthrough; read current; silicon pillar; vertical stacked gate cell; Buildings; Dielectrics; EPROM; Etching; Laboratories; Lithography; Nonvolatile memory; Secondary generated hot electron injection; Silicon; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347410

Filename

347410