Novel fault-tolerant circuits for configurable mass memories

Innovative orthogonal shuffle circuits, error correction by weighted codes, associative iterative repair, configurable modular architecture, and hierarchical organization in highly structured implementation are proposed for monolithic mass memories. Tests on experimental 40-Mb and 10-Mb monolithic CMOS static memories demonstrated read and write data rate of 120 MHz, module access time of 25 ns, power dissipation of 880 mW, mean time between failures of>0.5 Mh, data retention time of 10 years, and radiation hardness of 1 Mrad. The experimental memory devices are manufacturable with low-cost VLSI processing technologies which are normally used for digital logic circuits only. This work signifies that circuit innovations make possible the enlargement of chip sizes to wafer sizes without compromises in manufacturability and performance